A host (e.g., a memory controller) may perform partial writes to a dynamic random access memory device (DRAM) in which one or more of the bytes of write data are masked. In conventional systems (e.g., double data rate (DDR)1, DDR2, and DDR3), one or more dedicated data mask pins are used to transfer the data mask bits. Typically, the data mask pins are toggling at the same frequency as the data pins (e.g., on the data bus). A conventional system typically uses one data mask signal per byte lane of data. Thus, a ×4 or a ×8 device may have one data mask pin and a ×16 device may have two data mask pins.